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ASAHI KASEI
[AKD4641EN-A]
AKD4641EN-A
Evaluation board Rev.1 for AK4641EN
GENERAL DESCRIPTION The AKD4641 is an evaluation board for the AK4641, 16bit stereo CODEC with built-in Microphone-amplifier and 16bit Mono CODEC for Bluetooth Interface. The AKD4641 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D D/A). The AKD4641 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD4641EN-A --- Evaluation board for AK4641EN (Cable for connecting with printer port of IBM-AT, compatible PC and control software are packed with this. This control software does not support Windows NT.)
FUNCTION * DIT/DIR with optical input/output * BNC connector for an external clock input * 10pin Header for I2C control mode * On board headphone-amp (MAX4410) and speaker-amp (LM4889)
AVDD 5V Regulator MIC Jack AUXIN+ AUXINMOUT+ Bluetooth I/F MOUT+/MOUT LOUT ROUT HP Jack HP-amp MAX4410 SPK-amp LM4889 MOUT2 DIR AK4114 Opt In Opt Out MOUT10pin Header Audio I/F 10pin Header Clock Gen 3.3V Control Data 10pin Header BVDD DVDD AGND
AK4641
Figure 1. AKD4641 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual
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ASAHI KASEI
[AKD4641EN-A]
Evaluation Board Manual Operation sequence
1) Set up the power supply lines. 1-1) When AVDD, BVDD, DVDD and VCC are supplied from the regulator. (AVDD, BVDD, DVDD and VCC jack should be open.). See "Other jumper pins set up (page 9)". [REG] (red) [AVDD] (orange) [BVDD] (orange) [DVDD] (orange) [VCC] (orange) [H/SVDD] (orange) [AGND] (black) [DGND] (black) = 5V = open = open = open = open = 3.3V = 0V = 0V
: 3.3V is supplied to AVDD of AK4641 from regulator. : 3.3V is supplied to BVDD of AK4641 from regulator. : 3.3V is supplied to DVDD of AK4641 from regulator. : 3.3V is supplied to logic block from regulator. : for MAX4410 and LM4889 logic (typ.3.3V) : for analog ground : for logic ground
1-2) When AVDD, BVDD, DVDD and VCC are not supplied from the regulator. (AVDD, BVDD, DVDD and VCC jack should be open). See "Other jumper pins set up (page 9)". [REG] (red) [AVDD] (orange) [BVDD] (orange) [DVDD] (orange) [VCC] (orange) [H/SVDD] (orange) [AGND] (black) [DGND] (black) = "REG" jack should be open. = 2.6 3.6V : for AVDD of AK4641 (typ. 3.3V) = 2.6 3.6V : for BVDD of AK4641 (typ. 3.3V) = 2.6 3.6V : for DVDD of AK4641 (typ. 3.3V) = 2.6 3.6V : for logic (typ. 3.3V) = 2.6 3.6V : for MAX4410 and LM4889 logic (typ.3.3V) = 0V : for analog ground = 0V : for logic ground
Each supply line should be distributed from the power supply unit. DVDD and VCC must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4641 and AK4114 should be reset once bringing SW1, 2 "L" upon power-up.
Evaluation mode
1. Evaluation of 16bit stereo CODEC In case of AK4641 evaluation using AK4114, it is necessary to correspond to audio interface format for AK4641 and AK4114. About AK4641's audio interface format, refer to datasheet of AK4641. About AK4114's audio interface format, refer to Table 2 in this manual. (1-1) Evaluation of Recording block (MIC, ADC) using DIT of AK4114 (1-2) Evaluation of Playback block (HP, SPK, MOUT) using DIR of AK4114 (1-3) Evaluation of Loop Back (ADC DAC) using 16bit Mono CODEC (1-4) All interface signals including master clock are fed externally.
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ASAHI KASEI
[AKD4641EN-A]
(1-1) Evaluation of Recording block (MIC, ADC) using DIT of AK4114 PORT2 (DIT) and X2 (X'tal) are used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX141). Nothing should be connected to PORT1 (DIR) and PORT3 (Audio I/F), J12 (EXT). JP25 (EXT) is short. CM0 is set "H " and CM1 is set "L " for SW1, AK4114 is set X'tal mode.
JP24 XTI JP26 MCLK_SEL
JP27
JP30 BICK2
JP28 BICK_INV
BICK1
MCKO01 MCKO02 DIR
PORT DIR PORT
THR
INV
JP29 LRCK1
JP31 LRCK2
JP32 SDTI1
JP33 SDTI2
DIR
PORT DIR PORT
DIR
LOOP
DIT does not operate under fs = 32kHz, this mode corresponds to fs = 32kHz and over.
(1-2) Evaluation of Playback block (HP, SPK, MOUT) using DIR of AK4114 PORT1 (DIR) is used. Nothing should be connected to PORT3 (Audio I/F) and J12 (EXT). X1 (X'tal) is removed. JP25 (EXT) is short. CM0 is set "L " and CM1 is set "L " for SW1, AK4114 is set PLL mode.
JP24 XTI JP26 MCLK_SEL
JP27
JP30 BICK2
JP28 BICK_INV
BICK1
MCKO01 MCKO02 DIR
PORT DIR PORT
THR
INV
JP29 LRCK1
JP31 LRCK2
JP32 SDTI1
JP33 SDTI2
DIR
PORT DIR PORT
DIR
LOOP
DIR does not operate under fs = 32kHz, this mode corresponds to fs = 32kHz and over.
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ASAHI KASEI
[AKD4641EN-A]
(1-3) Evaluation of Loop Back (ADC DAC) using 16bit Mono CODEC X2 (X'tal) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (Audio I/F).
JP24 XTI JP26 MCLK_SEL
JP27
JP30 BICK2
JP28 BICK_INV
BICK1
MCKO01 MCKO02 DIR
PORT DIR PORT
THR
INV
JP29 LRCK1
JP31 LRCK2
JP32 SDTI1
JP33 SDTI2
DIR
PORT DIR PORT
DIR
LOOP
(1-4) All interface signals including master clock are fed externally. PORT3 (Audio I/F) and J12 (EXT) is used. Nothing should be connected to PORT1 (DIR). X2 (X'tal) is removed. JP25 (EXT) and R51 should be properly selected in order to much the output impedance of the clock generator.
JP24 XTI JP26 MCLK_SEL
JP27
JP30 BICK2
JP28 BICK_INV
BICK1
MCKO01 MCKO02 DIR
PORT DIR PORT
THR
INV
JP29 LRCK1
JP31 LRCK2
JP32 SDTI1
JP33 SDTI2
DIR
PORT DIR PORT
DIR
LOOP
JP28 (BICK_INV) is jumper which decides polarity of BICK, set "THR" or "INV" for audio interface format.
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ASAHI KASEI
[AKD4641EN-A]
2. Evaluation of 16bit Mono CODEC
(2-1) (2-2) (2-3) (2-4) (2-5) (2-6)
Set up jumper pins of BBICK clock Set up jumper pins of BSYNC clock Set up jumper pins of two types of data formats Evaluation of ADC (AUXIN) using 16bit Mono CODEC Evaluation of DAC (MOUT) using 16bit Mono CODEC Evaluation of Loop Back (ADC DAC) using 16bit Mono CODEC
(2-1) Set up jumper pins of BBICK clock Input frequency of BBICK can be set up in turn "32fs","64fs" or "128fs" from left.
JP18 BBICK_SEL
JP18 BBICK_SEL
JP18 BBICK_SEL
EXT 32fs 64fs 128fs
EXT 32fs 64fs 128fs
EXT 32fs 64fs 128fs
(2-2) Set up jumper pins of BSYNC clock Input frequency of BSYNC can be set up in turn "2fs" or "1fs" from left.
JP20 BSYNC_SEL1 JP20 BSYNC_SEL1
EXT 1fs
2fs
EXT
1fs
2fs
When an external clock through a BNC connector (J10: BBICK and J11: BSYNC) is supplied, select EXT on JP18 (BBICK_SEL) and JP20 (BSYNC_SEL) and short JP17 (XTE). JP22 (EXT1) and JP23 (EXT2) and R44 and R45 should be properly selected in order to much the output impedance of the clock generator.
(2-3) Set up jumper pins of two types of data formats (2-3-1) Set up jumper pins of "I2S"
JP21 BSYNC_SEL2 JP39 BBICK_INV
I2S
SHORT
THR
INV
(2-3-2) Set up jumper pins of "Short Format Sync"
JP21 BSYNC_SEL2 JP39 BBICK_INV
I2S
SHORT
THR
INV
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ASAHI KASEI
[AKD4641EN-A]
(2-3-3) Set up jumper pins of "MSB justified"
JP21 BSYNC_SEL2 JP39 BBICK_INV
I2S
SHORT
THR
INV
(2-4) Evaluation of ADC (AUXIN) using 16bit Mono CODEC PORT5 (Bth I/F) and X1 (X'tal) are used. Nothing should be connected to J10 (BBICK) and J11 (BSYNC). JP19 JP35 JP17 JP38 XTE BBICK2 CLK_SEL BBICK1
CLK
EXT
INT
PORT INT PORT
JP40 BSYNC1
JP36 BSYNC2
JP37 SDTI
INT
PORT INT PORT
PORT LOOP
(2-5) Evaluation of DAC (MOUT) using 16bit Mono CODEC PORT5 (Bth I/F) and X1 (X'tal) are used. Nothing should be connected to J10 (BBICK) and J11 (BSYNC). When an BSYNC through a PORT5 connector (Bth I/F) is supplied, open JP20 (BSYNC_SEL). JP19 JP35 JP17 JP38 XTE BBICK2 CLK_SEL BBICK1
CLK
EXT
INT
PORT INT PORT
JP40 BSYNC1
JP36 BSYNC2
JP37 SDTI
INT
PORT INT PORT
PORT LOOP
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ASAHI KASEI
[AKD4641EN-A]
(2-6) Evaluation of Loop Back (ADC DAC) using 16bit Mono CODEC X1 (X'tal) are used. Nothing should be connected to PORT5 ( Bth -I/F ), J10 (BBICK) and J11 (BSYNC).
JP17 XTE JP19 CLK_SEL JP38 BBICK1 JP35 BBICK2
CLK
EXT
INT
PORT INT PORT
JP40 BSYNC1
JP36 BSYNC2
JP37 SDTI
INT
PORT INT PORT
PORT LOOP
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ASAHI KASEI
[AKD4641EN-A]
DIP Switch set up
[SW1] : Mode Setting of AK4114 ON is "H", OFF is "L". No. 1 2 3 4 5 6 7 Name ON ("H") OFF ("L") AK4114 Audio Format Setting DIF0 See Table 2 DIF2 CM0 AK4114 AUTO (X'tal / PLL) Mode CM1 OCKS1 Fixed to "L" TST2 NC Table 1. Mode Setting for AK4534 and AK4114 Default ON ON OFF ON OFF OFF OFF
Mode 0 1 2 3
DIF2 DIF0 AK4114 DAUX AK4114 SDTO 0 0 24bit, MSB justified 16bit, LSB justified 0 1 24bit, MSB justified 24bit, LSB justified 1 0 24bit, MSB justified 24bit, MSB justified 1 1 24bit, I2S 24bit, I2S Table 2. Setting for AK4114 Audio Interface Format
CM0 0 1
UNLOCK PLL X'tal Clock source SDTO ON ON(Note) PLL RX OFF ON X'tal DAUX 0 ON ON PLL RX 2 1 0 1 ON ON X'tal DAUX 3 1 1 ON ON X'tal DAUX ON: Oscillation (Power-up), OFF: STOP (Power-down) Note : When the X'tal is not used as clock comparison for fs detection (i.e. XTL1,0= "1,1"), the X'tal is off.
Mode 0 1
CM1 0 0
Table 3. Clock Operation Mode select
No. 0 2 OCKS1 0 1 MCKO1 256fs 512fs MCKO2 256fs 256fs X'tal 256fs 512fs fs (max) 96 kHz 48 kHz
Table 4. Master Clock Frequency Select (Stereo mode)
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ASAHI KASEI
[AKD4641EN-A]
Other jumper pins set up
1. JP1 (GND): Analog ground and Digital ground OPEN : Separated. SHORT : Common. (The connector "DGND" can be open.) 2. JP3 (AVDD_SEL): AVDD of the AK4641 REG : AVDD is supplied from the regulator ("AVDD" jack should be open). < default > AVDD : AVDD is supplied from "AVDD " jack. 3. JP4 (BVDD_SEL): BVDD of the AK4641 AVDD : AVDD is supplied from "AVDD". < default > BVDD : BVDD is supplied from "BVDD " jack. 4. JP5 (DVDD_SEL): BVDD of the AK4641 BVDD : DVDD is supplied from "BVDD". < default > DVDD : BVDD is supplied from "BVDD " jack. 5. JP2 (D3.3V_SEL): VCC of logic DVDD : VCC is supplied from "DVDD". < default > VCC : VCC is supplied from "VCC " jack. 6. JP6 (LOUT/HP_SEL): Select analog signal of LOUT pin LOUT : Analog signal of LOUT pin is output from J1 (RCA) connector. < default > ROUT : Analog signal of LOUT pin is output from J2 (mini jack) connector. 7. JP7 (ROUT/HP_SEL): Select analog signal of ROUT pin LOUT : Analog signal of LOUT pin is output from J1 (RCA) connector. < default > ROUT : Analog signal of LOUT pin is output from J2 (mini jack) connector. 8. JP8 (SHDN_L): Left-Channel shutdown mode for MAX4410 OPEN : Left-Channel active mode. SHORT : Left-Channel shutdown mode. < default > 9. JP9 (SHDN_R): Right-Channel shutdown mode for MAX4410 OPEN : Right-Channel active mode. SHORT : Right-Channel shutdown mode. < default > 10. JP12 (MOUT2/SPK_SEL): Select analog signal of MOUT2 pin MOUT2 : Analog signal of MOUT2 pin is output from J7 (RCA) connector. < default > SPK : Analog signal of MOUT2 pin is output from speaker. 11. JP15 (SHDN_SPK): shutdown mode for LM4889 OPEN : Speaker active mode. SHORT : Speaker shutdown mode. < default > 12. JP34 (BSDTO): Please make use of open < default >
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ASAHI KASEI
[AKD4641EN-A]
The function of the toggle SW
Upper-side is "H" and lower-side is "L". [SW1] (DIR): Power down of the AK4114. Keep "H" during normal operation. Keep "L" when the AK4114 is not used. [SW2] (PDN): Power down of the AK4641. Keep "H" during normal operation.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when the AK4114 has some error.
I2C- bus Control Interface
The AK4641 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4 (CTRL) with PC by 10 wire flat cable packed with the AKD4641.
Connect PC
CSN SCL SDA
AKD4641
10 wire flat cable
10pin Connector
10pin Header
Figure 2. Connect of 10 wire flat cable
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ASAHI KASEI
[AKD4641EN-A]
Analog Input / Output Circuits
1. Input Circuits 1-1. MIC Input Circuit
J4 MIC EXT EXT
JP11 MIC INT
INT
Figure 3. MIC Input Circuit (1) Analog signal is input to INT pin via J4 connector.
JP11 MIC
INT
EXT
(2) Analog signal is input to EXT pin via J4 connector.
JP11 MIC
INT
EXT
1-2. AUXIN+ / AUXIN- Input Circuit
J5 AUXIN+ RCA R29 47k C27 1u AUXIN+ +
J6 AUXINRCA R30 47k
C29 1u AUXIN+
Figure 4. AUXIN+ / AUXIN- Input Circuits
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ASAHI KASEI
[AKD4641EN-A]
2. Output Circuits 2-1. LOUT / ROUT Output Circuit
LOUT HP
+
LOUT/HP_SEL JP6 LOUT
C21 22u
R19 220 R20 10k RCA
J1 LOUT
for HPL-amp ROUT/HP_SEL JP7 HP ROUT ROUT for HPR-amp C23 22u + R27 220 R28 10k RCA J3 ROUT
Figure 5. LOUT /ROUT Output Circuit 2-2. MOUT2 Output
MOUT2/SPK_SEL JP12 MOUT2 C30 22u MOUT2 SPK + R32 10k
R31 220 RCA
J7 MOUT2
for SPK-amp
Figure 6. MOUT2 Output Circuit
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ASAHI KASEI
[AKD4641EN-A]
2-3. MOUT+/- Output Circuit
C31 MOUT+ 22u MOUT+ MOUTR35 10k + JP13 MOUT+/-_SEL R33 220 RCA J8 MOUT+
C34 MOUT22u +
JP14 DIFF1
R39 R40 10k 100
J9 MOUT
2 2 1 3 3
JP16 DIFF2 R42 10k
R41 100
Figure 7. MOUT+/- Output Circuit
(1) Signal of MOUT+ pins are output from J8.
JP13 MOUT+/-_SEL JP14 DIFF1 JP16 DIFF2
MOUT+
MOUT-
(2) Signal of MOUT- pins are output from J8.
JP13 MOUT+/-_SEL JP14 DIFF1 JP16 DIFF2
MOUT+
MOUT-
(3) Signal of MOUT+ / - pins are output from J9.
JP13 MOUT+/-_SEL JP14 DIFF1 JP16 DIFF2
MOUT+
MOUT-
AKM assumes no responsibility for the trouble when using the above circuit examples. - 13 2006/03
1
ASAHI KASEI
[AKD4641EN-A]
Control Software Manual Set-up of evaluation board and control software
This evaluation board supports to I2C control. 1. Set up the AKD4641 according to previous term. 2. Connect IBM-AT compatible PC with AKD4641 by 10-line type flat cable (packed with AKD4641). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AK4641 Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "akd4641.exe" to set up the control program. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Setup" button. 3. Click "Write default" button. 4. Then set up the dialog and input data.
Explanation of each buttons
1. [Port Reset] : 2. [Write default] : 3. [All Read] : 4. [All Write] : 5. [Function1] : 6. [Function2] : 7. [Function3] : 8. [Function4] : 9. [Function5] : 10.[Write] : 11.[Read] : 12.[SAVE] : 13.[OPEN] : Set up the port. When this is pushed, the printer port or USB port is selected automatically. Initialize the register of the AK4641 Read all registers of the AK4641. Write all registers that is currently displayed Dialog to write data by keyboard operation. Dialog to evaluate IPGA and ATTL/ATTR. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Dialog to write data by mouse operation. Read data by mouse operation. Save the current register setting. Write the save values to all register.
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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ASAHI KASEI
[AKD4641EN-A]
Explanation of each dialog 1. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Data Box: Input register address in 2 figures of hexadecimal. Input register data in 2 figures of hexadecimal.
If you want to write the input data to AK4641, click "OK" button. If not, click "Cancel" button.
2. [Function2 Dialog] : Dialog to evaluate IPGA and ATTL/ATTR
This dialog corresponds to only addr=0BH and 0CH, 0DH. Address Box: Input register address in 2 figures of hexadecimal. Start Data Box: Input start data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4641 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4641, click "OK" button. If not, click "Cancel" button.
3. [Write Dialog] : Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the "Write" button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4641, click "OK" button. If not, click "Cancel" button.
4.[Save] and [Open] 4-1. [Save]
Save the current register setting data. The extension of file name is "akr". (Operation flow) (1) Click [Save] Button. (2) Set the file name and push [Save] Button. The extension of file name is "akr".
4 -2. [Open]
The register setting data saved by [Save] is written to AK4643. The file type is the same as [Save]. (Operation flow) (1) Click [Open] Button. (2) Select the file (*.akr) and Click [Open] Button.
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ASAHI KASEI
[AKD4641EN-A]
5.[Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [Start] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file name is "aks".
Figure 1. Window of [F3]
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ASAHI KASEI
[AKD4641EN-A]
6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the window as shown in Figure2 opens.
Figure 2. [F4] window
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ASAHI KASEI
[AKD4641EN-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks). The sequence file name is displayed as shown in Figure 3.
Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The sequence file names can assign be saved. The file name is *.ak4.
[OPEN] : The sequence file names assign that are saved in *.ak4 are loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function. (2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
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ASAHI KASEI
[AKD4641EN-A]
7.[Function5 Dialog]
The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When [F5] button is clicked, the following window as shown in Figure 4 opens.
Figure 4. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 5. (2) Click [WRITE] button, then the register setting is executed.
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ASAHI KASEI
[AKD4641EN-A]
Figure 5. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The register setting file names assign can be saved. The file name is *.ak5. [OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side. (2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to reflect the change.
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ASAHI KASEI
[AKD4641EN-A]
Measurement Result 1. 16bit stereo CODEC
[Measurement condition] * Measurement unit * MCLK * BICK * fs * Bit * Power Supply * Measurement Filter * Temperature [Measurement Results]
1.ADC (INT) characteristics (MIC Gain = +20dB, IPGA = 0dB, ALC1 = OFF, MIC [dB] THD+N DR S/N 20kHzLPF (-1dB) 20kHzLPF + A-weighted 20kHzLPF + A-weighted 83.3 86.1 86.1 IPGA ADC) IPGA ADC)
: Audio Precision, System Two : 256fs : 64fs : 44.1kHz : 16bit : AVDD=BVDD=DVDD=3.3V : 20Hz 20kHz : Room
2.ADC (EXT) characteristics (MIC Gain = +20dB, IPGA = 0dB, ALC1 = OFF, EXT [dB] THD+N DR S/N 20kHzLPF (-1dB) 20kHzLPF + A-weighted 20kHzLPF + A-weighted 83.3 86.1 86.1
3. ADC (AUXIN+ / AUXIN-) characteristics ( MICAD =0, AUXIN+/AUXIN[dB] THD+N DR S/N 20kHzLPF (-1dB) 20kHzLPF + A-weighted 20kHzLPF + A-weighted 87.6 91.1 91.1
ADC)
4. DAC (LOUT/ROUT) characteristics (RL=10k, DAC LOUT/ROUT) L[dB] R[dB] THD+N DR S/N 20kHzLPF (-3dB) 20kHzLPF + A-weighted 20kHzLPF + A-weighted 86.4 89.4 90.7 86.4 89.5 91.0
5. DAC (MOUT+ / MOUT-) characteristics (RL=20k, DAC MOUT+ / MOUT-) MOGN=0[dB] MOGN=1[dB] THD+N DR S/N 20kHzLPF (-3dB) 20kHzLPF + A-weighted 20kHzLPF + A-weighted 87.7 90.9 93.0 MIX [dB] 87.9 90.7 92.7 74.0 76.8 77.0 MOUT2)
6. DAC (MOUT2) characteristics (RL=10k, DAC THD+N DR S/N 20kHzLPF (-3dB) 20kHzLPF + A-weighted 20kHzLPF + A-weighted
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ASAHI KASEI
[AKD4641EN-A]
2. 16bit Mono CODEC
[Measurement condition] * Measurement unit * BBICK * fs * Bit * Power Supply * Measurement Filter * Temperature [Measurement Results]
1. ADC (AUXIN) characteristics ( MICAD =0, AUXIN [dB] THD+N DR S/N 20kHzLPF (-1dB) 20kHzLPF + A-weighted 20kHzLPF + A-weighted 78.5 88.7 88.9 MOUT, ATT = 0dB) [dB] 78.9 91.4 92.0 Mixer ADC, AUX Volume = 0dB)
: ROHDE & SCHWARZ, UPD05 : 32fs : 8kHz : 16bit : AVDD=BVDD=DVDD=3.3V : 20Hz 4kHz : Room
2. DAC (MOUT) characteristics (RL=20k, DAC THD+N DR S/N 20kHzLPF (-0dB) 20kHzLPF + A-weighted 20kHzLPF + A-weighted
3. Loop-back (AUXIN THD+N DR S/N
ADC
DAC
MOUT)
[dB] 76.7 87.9 88.0
20kHzLPF (-3dB) 20kHzLPF + A-weighted 20kHzLPF + A-weighted
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ASAHI KASEI
[AKD4641EN-A]
3. 16bit stereo CODEC PLOT DATA 3-1. ADC (MIC IPGA ADC) PLOT DATA
AKM
-60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -120 -110 -100 -90 -80 -70 -60 dBr -50 -40 -30 -20 -10 +0
AK4641 ADC(INT) THD+N vs. Input Level VDD=3.3V, fs=44.1kHz, fin=1kHz
Figure 1. THD+N vs. Input Level
AKM
-60 -62 -64 -66 -68 -70 -72 -74 -76 d B F S -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
AK4641 ADC(INT) THD+N vs. Input Frequency VDD=3.3V, fs=44.1kHz, Input=-1dB
Figure 2. THD+N vs. Input Frequency
- 23 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
AK M
+0 -10 -20 -30 -40 d B F S -50 -60 -70 -80 -90 -100 -110 -120 -120
AK 4641 AD C (INT) Linearity V D D=3.3V, fs=44.1kHz, fin=1kHz
-110
-100
-90
-80
-70
-60 dB r
-50
-40
-30
-20
-10
+0
Figure 3. Linearity
AK M
-0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -5 20
AK 4641 A D C (INT) Frequency R esponse VD D =3.3V, fs=44.1kHz, Input=-1dB
d B F S
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 4. Frequency Response
- 24 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100
AK4641 ADC(INT) FFT Plot VDD=3.3V, fs=44.1kHz, fin=1kHz, Input=-1dB
200
500 Hz
1k
2k
5k
10k
20k
Figure 5. FFT Plot ( Input level=-1dBFS)
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
AK4641 ADC(INT) FFT Plot VDD=3.3V, fs=44.1kHz, fin=1kHz, Input=-60dB
Figure 6. FFT Plot ( Input level=-60dBFS )
- 25 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100
AK4641 ADC(INT) FFT Plot VDD=3.3V, fs=44.1kHz, Input=no signal
200
500 Hz
1k
2k
5k
10k
20k
Figure 7. FFT Plot ( No signal )
- 26 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
3-2. DAC (DAC
AKM
-60 -62 -64 -66 -68 -70 -72 -74 -76 d B r A -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -120 -110
Mono Out) PLOT DATA
AK4641 DAC(LOUT/ROUT) THD+N vs. Input Level VDD=3.3V, fs=44.1kHz, fin=1kHz
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 8. THD+N vs. Input Level
AKM
-60 -62 -64 -66 -68 -70 -72 -74 -76 d B r A -78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
AK4641 DAC(LOUT/ROUT) THD+N vs. Input Frequency VDD=3.3V, fs=44.1kHz, Input Level=-3dB
Figure 9. THD+N vs. Input Frequency
- 27 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
AKM
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -120
AK4641 DAC(LOUT/ROUT) Linearity VDD=3.3V, fs=44.1kHz, fin=1kHz
d B r A
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 10 Linearity
AK M
+ 0.5 + 0.4 + 0.3 + 0.2 d B r A + 0.1 +0 -0.1 -0.2 -0.3 -0.4 -0.5 2k
AK 4641 D A C (LO UT/R O UT) Frequency R esponse VD D =3.3V, fs=44.1kHz, Input=-0dB
4k
6k
8k
10k Hz
12k
14k
16k
18k
20k
Figure 11. Frequency Response
- 28 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100
AK4641 DAC(LOUT/ROUT) FFT Plot VDD=3.3V, fs=44.1kHz, fin=1kHz, Input Level=-3dB
200
500 Hz
1k
2k
5k
10k
20k
Figure 12. FFT Plot ( Input level=-3dBFS )
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
AK4641 DAC(LOUT/ROUT) FFT Plot VDD=3.3V, fs=44.1kHz, fin=1kHz, Input=-60dB
Figure 13. FFT Plot ( Input level=-60.0dBFS )
- 29 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100
AK4641 DAC(LOUT/ROUT) FFT Plot VDD=3.3V, fs=44.1kHz, Input=no signal
200
500 Hz
1k
2k
5k
10k
20k
Figure 14. FFT Plot ( No signal )
AKM
+0 -10 -20 -30 -40 -50 -60 d B r A -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 20 50 100 200 500 1k Hz 2k 5k 10k 20k 50k 100k
AK4641 DAC(LOUT/ROUT) FFT Plot VDD=3.3V, fs=44.1kHz, Input = no signal
Figure 15. Out-of-band Noise
- 30 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
AK M
-60 -65 -70 -75 -80 -85 d B -90 -95 -100 -105 -110 -115 -120 20
A K4641 D AC (LO UT/R O UT) C rosstalk VD D =3.3V, fs=44.1kHz, Input=-0dB
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 16. Crosstalk Plot
- 31 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
4. 16bit Mono CODEC PLOT DATA 4-1. ADC (AUXIN Mixer ADC) PLOT DATA
Figure 17. THD+N vs. Input Level
Figure 18. THD+N vs. Input Frequency
- 32 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
Figure 19. Linearity
Figure 20. Frequency Response
- 33 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
Figure 21. FFT Plot ( Input level=-1dBFS)
Figure 22. FFT Plot ( Input level=-60dBFS )
- 34 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
Figure 23. FFT Plot ( No signal )
- 35 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
4-2. DAC (DAC
Mono Out ) PLOT DATA
Figure 24. THD+N vs. Input Level
Figure 25. THD+N vs. Input Frequency
- 36 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
Figure 26 Linearity
Figure 27. Frequency Response
- 37 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
Figure 28. FFT Plot ( Input level=-0dBFS )
Figure 29. FFT Plot ( Input level=-60.0dBFS )
- 38 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
Figure 30. FFT Plot ( No signal )
- 39 -
2006/03
ASAHI KASEI
[AKD4641EN-A]
Revision History Date (YY/MM/DD) 05/11/29 06/03/13 Manual Revision KM082000 KM082001 Board Revision 0 1 Reason First Edition Update Contents
Change of a figure & circuit
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
- 40 -
2006/03
A
B
C
D
E
DGND
E
JP1 GND
AGND MOUT+ AUXINMOUTAUXIN+ LOUT
REG(+5V) T1 TA48M33F
GND IN OUT
REG C2 0.1u C3 + 47u
E
C1 0.1u
EXT CN1
36 35 34 33 32 31 30 29 28
AGND
DVDD0 JP2 DVDD D3.3V_SEL
2
VCC(D3.3V) L1
1
D3.3V VCC
R1 2.2k U1
C4 1u
35
C5 1u
C6 47u
D
36
34
33
AUXIN-
AUXIN+
MOUT+
MOUT-
EXT
MDT
MICOUT
LOUT
AIN
CN2
32
31
30
29
28
+
Short
DGND
1
1
MPE
R2
2
2.2k
2 MPI MOUT2 26 26
C7 1u INT
3 3 INT TST2 25 25
REG
4
4
VCOM
C8 2.2u AVDD
C
+
C9 0.1u
5 AVSS
L2
1 2
6
C12 47u
+
Short
AVDD
AVDD0
7 7 BVDD BSDTI 21
C13 10u
8
9
9
AVDD0 JP4 BVDD_SEL BVDD L3
1
B
10
11
12
13
14
15
16
17
2
BVDD0 BVDD R8 51 R9 51 R10 51 R11 51 R12 51 R13 51 R14 51 R15 51
B
C18 47u
+
Short
10
11
12
13
14
15
16
17
AGND BVDD0 JP5 DVDD_SEL CN4
4641_LRCK
TST1
4641_SDTO
DVDD L4
1 2
BVDD
R16(short) DVDD1
C19
A
+
Short
DVDD DVDD0
47u
4641_MCKI
4641_PDN
4641_SDTI
4641_BICK
SCL
SDA
18
18
AVDD
MCLK
SDTO
LRCK
C17 470n
VCOC TST1 BICK SDTI PDN SDA SCL
DVDD
19
R7 5.1k
AGND
A
B
C
+ +
AGND
+
REG
JP3 AVDD_SEL
5
C10 C11 10u 0.1u
6 AVDD BSDTO 22
+
C14 0.1u
8 BVSS DVSS 20 20
+
+
CN3
ROUT 27 27
D
ROUT
MOUT2
TST2
+ 51 R3
BBICK 24 24
BBICK
AK4641
51 R4
BSYNC 23 23
BSYNC
C
51 R5
22
4641_BSDTO
51 R6
21
BSDTI
C15 0.1u
C16 10u
19
DVDD1
A
Title Size Document Number
AKD4641
AK4641
Sheet
E
Rev
A3
Date:
D
A 1
of
Friday, November 25, 2005
6
A
B
C
D
E
+
LOUT/HP_SEL JP6 LOUT LOUT
E
HP
R20 10k
+
RCA
C22 1u
+
C21 22u
R19 220
J1 LOUT
C20 1u
R17 10k
R18 10k
R21 10k
R22 10k
E
U2
10 13 INL INR SHDNL SHDNR SVDD PVDD C1P C1N PVSS PGND SVSS SGND OUTL OUTR 8 11
R23 (short) R24 (short)
ROUT/HP_SEL JP7 HP ROUT ROUT
C23 22u +
R27 220 R28 10k RCA
J3 ROUT
H/SVDD R25 20k JP8 SHDN_L R26 20k JP9 SHDN_R + C24 2.2u + C25 2.2u + C26 2.2u
1 12 9 2 3 5 6 4 7 14
J2 HP
J4 MIC
D
EXT
EXT
JP10 SHDN
MAX4410
D
JP11 MIC INT H/SVDD C27 1u AUXIN+
1 1 2
INT J5 AUXIN+ RCA R29 47k
H/SVDD
+ C28 47u
2
L5 (short)
+ +
J6 AUXINC
C29 1u AUXIN+ + R30 47k
RCA
MOUT2/SPK_SEL JP12 MOUT2 C30 22u MOUT2 SPK + R32 10k
R31 220 RCA
J7 MOUT2
C
C31 MOUT+ 22u +
JP13MOUT+/-_SEL MOUT+ MOUTR35 10k R33 220 RCA C33 0.47u + R36 20k J8 MOUT+
B
C34 + MOUT22u
JP14 DIFF1
H/SVDD R37 20k R39 R40 10k 100
2
J9 MOUT
2 1 3 3
JP15 SHDN_SPK
JP16 DIFF2 R42 10k
R41 100
1
H/SVDD C36 + 1u
A
A
B
C
+
C32 100p
R34 20k U3
3 4 2 1 6 +IN -IN Vo1 Vo2 5 8
SPK1 CN5
2
B
020S16 R
BYPASS SHUTDOWN VDD GND
1
R38 (short) + C35 1u
7
L
LM4889
A
Title Size Document Number
AKD4641
Input/Output
Sheet
E
Rev
A3
Date:
D
A 2
of
Friday, November 25, 2005
6
A
B
C
D
E
E
4.096MHz X1
1 2
E
R43 1M
U4A
1 2 3
U4B
4
74HCU04 JP17 XTE C37 15p C38 15p
74HCU04
D
D
MCLK_256fs 512fs 10
11
U5
CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1
CLK
C
JP19 CLK_SEL
256fs 128fs 64fs 32fs EXT 2fs 1fs
JP18 EXT_BBICK
EXT J10 BBICK
BBICK_SEL
C
JP20 EXT BSYNC_SEL1 U6A
1 3 2
R44 51 JP22 EXT1
74VHC4040
I2S SHORT
JP21 BSYNC_SEL2 EXT_BSYNC
74AC08
B
D3.3V J11 BSYNC
2 3 D CLK CL Q 6
B
U7A
Q 5 12 11 D CLK
10
U7B
Q 9
PR
4
CL
R45 51 JP23 EXT2 PORT_BSYNC U8A
1 2
PR
Q
8
1
74AC04
A
13
74AC74
74AC74
A
Title Size Document Number
AKD4641
CLOCK_Bth
Sheet
E
Rev
A3
Date:
A B C D
A 3
of
Wednesday, July 23, 2003
6
A
B
C
D
E
JP26 MCLK_SEL MCKO1 JP27 BICK1 DIR U12
E
DIR_MCLK1 DIR_MCLK2
MCKO2 DIR_BICK U13
PORT U19A
2 1 19
E
4641_MCKI
11
Y8
A8
9
1
G1
VCC
20
D3.3V C53 0.1u
JP28 BICK_INV INV 4641_BICK
12 Y7 A7 8
74HC14
G2 GND 10
THR
7
4641_LRCK
13
Y6
A6
JP29 LRCK1 DIR PORT
2
A1
Y1
18
DIR_LRCK
3 A2 Y2 17
4641_SDTI
14
Y5
A5
6
JP30 BICK2 DIR PORT JP31 LRCK2 DIR PORT
MCLK BICK LRCK SDTI VCC
PORT3
1 2 3 4 5 10 9 8 7 6
Audio I/F R52 D3.3V 10k SDTO JP32 SDTI1 LOOP
D
15
Y4
A4
5
4
A3
Y3
16
R53 100k
16
D
Y3
A3
4
5
A4
Y4
15
17
Y2
A2
3
6
A5
Y5
14
DIR
18 Y1 A1 2 7 A6 Y6 13
DIR_SDTI
10
GND
G2
19
8
A7
Y7
12
C54 0.1u
20 VCC G1 1 9 A8 Y8 11
74LVC541
74HC541 JP33 SDTI2
C
D3.3V
C
4641_SDTO
B
D3.3V R54 R56 R58 10k 10k 10k R55 R57 R59 470 470 470
2 3 5 6 11 10 14 13 1 15
U15
1A 1B 2A 2B 3A 3B 4A 4B A/B G 1Y 2Y 3Y 4Y 4 7 9 12 1
B
TST1 SCL SDA
D3.3V
2
D2 HSU119
R60 10k U9C
5 6 9
U9D
8
PORT4
1 2 3 4 5 10 9 8 7 6
TST2N CSN SCL SDA CDTO
4641_PDN
74LVC157
L
3 1
H SW2 PDN C55 0.1u
74HC14
74HC14
CTRL D3.3V
A
JP34 BSDTO BSDTO R62 10k U16A
1 2
R61 1.8k
Title Size Document Number
2
A
74LVC07
AKD4641
LOGIC_AUDIO
Sheet
E
Rev
A3
Date:
A B C D
A
of
Wednesday, July 23, 2003
5
6
A
B
C
D
E
E
U17
U18
E
BBICK
11
Y8
A8
9
1
G1
VCC
20
D3.3V C56 0.1u MCLK_256fs PORT5
1 2 3 4 5 10 9 8 7 6
BSYNC
12
Y7
A7
8
19
G2
GND
10
BSDTI
13
Y6
A6
7
2
A1
Y1
18
JP35 BBICK2 INT PORT JP36 BSYNC2 INT PORT
14
Y5
A5
6
R63 100k
MCLK BBICK BSYNC BSDTI VCC
3
A2
Y2
17
Bth I/F R64
15
D
Y4
A4
5
4
A3
Y3
16
PORT_BSYNC 10k
16 Y3 A3 4 5 A4 Y4 15
D3.3V BSDTO
D
17
Y2
A2
3
6
A5
Y5
14
JP37 SDTI
18 Y1 A1 2 7 A6 Y6 13
PORT LOOP
10
GND
G2
19
8
A7
Y7
12
C57 0.1u
20 VCC G1 1 9 A8 Y8 11
C
74LVC541
74HC541 4641_BSDTO
C
D3.3V JP39 BBICK_INV INV THR U19B
4 3
JP38 BBICK1 INT PORT
EXT_BBICK
74HC14
JP40 BSYNC1 INT PORT
EXT_BSYNC
B
B
U6B
4 6 5 5
U4C
6 5
U11C
6 11
U9E
10 3
U16B
4 3
U8B
4
74AC08 U6C
9 8 10 9
74HCU04 U4D
8 9
74HC04 U11D
8 13
74HC14 U9F
12 5
74LVC07 U16C
6 5
74AC04 U8C
6
74HCU04 U4E
11 10 11
74HC04 U11E
10 5
74HC14 U19C
6 9
74LVC07 U16D
8 9
74AC04 U8D
8
74AC08 U6D
12 11 13
74HCU04 U4F
13 12 13
74HC04 U11F
12 9
74HC14 U19D
8 11
74LVC07 U16E
10 11
74AC04 U8E
10
for 74AC02,74AC74,74HC04,74HC14,74HC14,74AC4040,74HCU04,74LVC07,74LVC157,74AC04 D3.3V
74AC08
A
74HCU04
74HC04
11
74HC14 U19E
10 13
74LVC07 U16F
12 13
74AC04 U8F
12
A
74HC14 U19F
13 12
74LVC07
74AC04 C58 0.1u C59 0.1u C60 0.1u C61 0.1u C62 0.1u C63 0.1u C64 0.1u C65 0.1u C66 0.1u C67 0.1u + C68 47u
Title Size Document Number
AKD4641
LOGIC_Bth
Sheet
E
74HC14
Rev
A3
Date:
C D
A 6
of
Wednesday, July 23, 2003
6
A
B
A
B
C
D
E
C39 C40 0.1u 0.1u D3.3V
1
D3.3V L6 (short)
E
2
R46 10k U9A
2 1 4
2
PORT1
VCC GND OUT 3 2 1
C41 0.1u R47 470 C42 10u D3.3V +
U9B
3
3
C44 0.1u
C43 0.1u
2
1
TORX141
74HC14
74HC14
L
1
D1 HSU119
E
H SW1 DIR
C45 0.47u
R48 18k
48
46
44
47
43
42
41
39
45
D
DIF0 DIF2 CM0 CM1 OCKS1 TST2
SW3
1 2 3 4 5 6 7 14 13 12 11 10 9 8
U10
TEST1
40
38
AVSS
VCOM
AVDD
INT1
RX3
RX2
RX1
RX0
NC
NC
R
37
D
U11A
INT0 36 1 2
R49 1k
2
LED1 ERF
1
1
IPS0
D3.3V
74HC04
2 NC OCKS0 35
MODE RP1
7 6 5 4 3 2 1
3
DIF0
OCKS1
34
OCKS1
CM0 CM1 OCKS1 TST2 U11B
3 4
4
TEST2
CM1
33
CM1
5
47k
C
DIF1
CM0
32
TST2N
6 NC
CM0
C
74HC04
1
7
DIF2
AK4114
PDN
31
C46 10p
XTI 30
JP24 XTI
J12 R5051 EXT
X2 11.2896MHz
IPS1 XTO 2 8 29
C47 10p
R51 51 JP25 EXT
9
P/SN
DAUX
28
SDTO
10
XTL0
MCKO2
27
DIR_MCLK2
11
B
XTL1
BICK
26
DIR_BICK
B
12
VIN MCKO1 COUT UOUT DVDD BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1
SDTO
25
DIR_SDTI
13
14
15
16
17
18
19
20
21
22
23
C48 0.1u +
C49 0.1u +
24
DIR_LRCK
DIR_MCLK1
C50 10u D3.3V PORT2
A
C51 10u D3.3V
A
IN VCC GND
3 2 1
D3.3V C52 0.1u
Title Size Document Number
TOTX141
AKD4641
DIR/DIT
Sheet
E
Rev
A3
Date:
A B C D
A 4
of
Wednesday, July 23, 2003
6

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